This appendix provides an overview of the WPC hardware, in terms of its capabilities and how software is able to control everything in the machine.
WPC pinball machines contain a number of circuit boards, some that are intelligent with microprocessors, and others that are passive. One of these, the CPU board, is the master and houses the main microprocessor, a Motorola 6809 running at 2MHz. All other boards are connected to this one via ribbon cables. The functionality is spread across multiple boards to make maintenance easier and to isolate faults. These data cables carry 5V, generally active low signals. Inputs read as high (inactive) when the cables are disconnected.
From 1990-1999, six different generations of machines were produced, which differed only slightly. In order of appearance:
The initial generation, which used 2 16-character alphanumeric displays, Each character is comprised of 14 line segments, a comma, and a period.
In addition to the CPU board, there is a power driver board which handles all of the high voltage I/O, and an alphanumeric controller board, which translates CPU commands into the proper signals that the displays need. There is also a separate sound board.
In the second generation, the alphanumerics are replaced by a dot matrix controller/display (DMD), which has 128x32 pixels. The display expects a serial bitstream and must be continously refreshed. The controller board stores up to 16 frames in its own RAM and handles the refresh. It connects to the main CPU board which writes the data. The display refreshes at 122Mhz.
Here, the flipper switches and drive transistors are moved from the regular switch matrix and power driver board onto a separate board, called the Fliptronic Board. There are Fliptronic I and Fliptronic II boards but they appear the same to software.
This frees up several of the switch matrix entries previously used for flipper buttons for other purposes. The flipper-related circuitry on the power driver board goes unused.
With the DCS generation, the sound board is radically improved, replacing the synthesizer chip and low-quality analog circuits with a DSP supporting high fidelity, stereo, multi-channel sound.
A security PIC chip is added between the ASIC and the switch matrix inputs. The CPU no longer reads the switch data directly; it sends commands to the PIC which then reads the data. The PIC requires some special cryptic codes to be sent otherwise it will not return valid switch data, making the game unplayable.
The functions of the circuit boards are combined into fewer boards, using FPGAs to replace many of the discrete TTL components. Functionally it is not much different, although the CPU addresses for many of the functions changed. The WPC ASIC remained the same, but its outputs are connected to the other circuit boards in slightly different ways.
The CPU board contains the main processor: a Motorola 68B09E, running at 2Mhz. It is an 8-bit/16-bit CPU with a 64KB address space. Bank switching is required to address more than 64KB. On reset, location 0xFFFE is read to determine the address of the first instruction.
8KB of RAM is located at physical address 0x0000. When power is turned off, three AA batteries on the CPU board maintain the state of the RAM.
The game ROM size varies from 128KB to 1MB, depending on the game. The hardware supports a maximum of 1MB; this upper limit was used in all of the later models to accommodate more and more graphics. The uppermost 32KB is permanently mapped into the 64KB address space at address 0x8000 and contains the core operating system functions. The remaining parts of the ROM must be bank switched in, 16KB at a time; only one 16KB bank at a time is visible at address 0x4000.
The WPC ASIC is the heart of the system and is essentially a giant address decoder. It combines a lot of the functionality that was performed by PIAs and TTL logic in earlier solid state games. All read/write requests from the CPU are first seen by the ASIC, which can then either respond to it directly if it is an internal function, or forward the request to another device. RAM and ROM requests cause those devices enables to be asserted. For I/O, it may be more complicated and cause I/O to other circuit boards.
The system blanking circuit protects the circuit boards during system initialization. The ASIC generates the BLANKING signal which is carried to all of the other boards. When asserted, BLANKING means to disable all output circuits.
Blanking is initially asserted by the ASIC at powerup, so that no lamps or solenoids can be turned on, regardless of the states of the outputs from the CPU board. Once the CPU has initialized, it writes to the ASIC to disable blanking; then the other register outputs take effect.
LED 3 is controlled by writing to bit 7 of the WPC_LEDS register; this register can also be read to get the current LED state. The OS toggles this bit periodically to indicate that the system is alive. It is also used during early fatal errors as a primitive way of providing an error message.
The ASIC has a builtin watchdog timer which will reset the CPU board if software does not restart it periodically. The expiration seems to be on the order of 1 or 2ms.
FreeWPC restarts the watchdog on every periodic interrupt, every 1ms. During initialization, when interrupts are disabled, it also restarts it occasionally.
The ASIC has a bit shifter which offloads the CPU from having to calculate shifts using multiple CPU instructions. The 6809 does not have a native shift instruction for more than 1 bit at a time.
The bit shifter is used to optimize bit-level operations (set, clear, test, and toggle). This is particularly useful on WPC because RAM is scarce; many variables are stored as bits to save space.
As an address decoder, the WPC ASIC is capable of restricting access to any part of the address space. The memory protection circuit lets you lock a portion of the system RAM as read-only, so that writes to those addresses are effectively no-ops.
The feature can be enabled/disabled, and the size of the protected region can also be specified. The region must reside in the uppermost part of RAM and must be a power of 2 in size.
FreeWPC uses memory protection to guard adjustments, audits, and some other vital data.
The time-of-day device maintains the current calendar time. It has two read/write registers, which stores hours and minutes. The clock continues to count even when power is turned off.
Software maintains the calendar time in nonvolatile memory.
The high resolution timer is not currently used by FreeWPC. It allows for sub-millisecond accuracy, and was only used in alphanumeric games to do display dimming.
The bank switch register allows you to select which portion of the ROM is mapped to the banked region of the physical address space, at 0x4000. Only the lower 6-bits of the register are used, allowing for up to 64 pages. These bits become the uppermost address lines sent to the ROM device.
All of the switch inputs terminate directly on the CPU board. This includes up to 64 playfield switches, arranged in an 8x8 matrix; 8 direct inputs used for service buttons and coin switches; and several jumpers/DIP switches used for configuring some factory defaults.
All of the other I/O is located on other boards, which are connected to the CPU board via ribbon cables. Generally on these cables, one side of the pins are connected to ground, while the others contain actual inputs/outputs. All logic values measure 0V for a '0', and +5V for a '1'. Inputs have pullup resistors so that reading the signal while the cable is not connected will return '1'. All generations of WPC use the same 17x2 pin connector to the power driver board, which controls lamps and general solenoids. Display, sound, and flipper interfaces differ somewhat between generations.
Special I/O boards exist to drive other miscellaneous devices like ticket dispensers or a printer. These were addons that are not typically installed in all machines.
The ASIC generates the reset, IRQ, and FIRQ signals which are sent to the CPU.
The 6809 instructions to generate soft interrupts — swi, swi2, and swi3, are not used. The handlers for those vectors all throw fatal errors.
The ASIC drives the CPU reset signal. This signal is active low; normally the reset line is high. The ASIC will pull reset low when the watchdog timer expires.
IRQ is generated 976 times per second, about once every 1.02ms. An oscillator on the CPU board generates the frequency. The periodic interrupt can be disabled/enabled by writing to the ASIC's WPC_ZEROCROSS_IRQ_CLEAR register. Separately, IRQ can be masked/unmasked by writing to the 6809's condition-code (CC) register.
FIRQ can be generated in two ways: from the dot matrix controller after a certain scanline is redrawn, or from the high-performance timer. When an FIRQ is received, the CPU has to determine which of these occurred to determine how to process it.
The DMD controller can interrupt via FIRQ when a particular scanline of the display has just been sent to the display. This can be used to tell the CPU when to display a new frame.
The high precision timer can interrupt when its value reaches zero.
Either of these can be enabled/disabled individually, in addition to masking the interrupt at the processor.
The CPU's NMI input is not used and is connected to Vcc.
The power driver board contains all of the high power circuitry. It has no intelligent parts and is controlled completely by the CPU board over a short ribbon cable. It houses the drive transistors which switch current to the high power devices, along with fuses and other power-related circuitry.
WPC supports up to 64 individually controllable lamps. The lamps are arranged in an 8x8 matrix. At any given instant, only 8 of the lamps can receive power. A column strobe is written to determine which set of 8 lamps is being addressed. A row output is written to specify the on/off states of that set of lamps. Software must repeatedly strobe each of the lamp columns in order to update all 64 lamps.
The filaments in incandescent lamps operate at around 6V. The lamp circuitry switches a much higher 18V, but strobing only enables that voltage for 1/8 of the time, and filaments do not instantly turn off when power is removed, so no flicker is perceived. LEDs do not have this property and this explains the flicker that is often seen when people replace normal bulbs with LEDs.
All versions of the power driver board support 28 controlled outputs for solenoids, motors, etc. These are divided into four groups: 8 high power drivers, 8 low power drivers, 8 flashlamp drivers, and 4 general purpose drivers. Each bank operates at a different voltage, somewhere between 20V and 50V.
The CPU board enables/disable a driver by writing a command to the power driver board. All values are latched on the driver board and thus retain their states until the CPU changes them. The latches are not readable, so software must maintain the last value written in RAM. A CPU board reset will assert a blanking signal to reset the latches; this helps in the event of a software crash.
On WPC-95, 4 additional low voltage outputs running at 5V are added to the general purpose group, which can be used for miscellaneous I/O like small DC motors.
The GI circuitry allows for 5 strings of up to 18 lamps each. These are separate from the controlled lamps described previously; individual lamps are not controllable, only entire strings of lamps. Each string can independently be turned on and off by a triac. The lamps all run off 6.3V AC.
Starting with WPC-95, two of the GI strings are always on and not under software control, saving the cost of the triacs, but eliminating the ability to dim them.
When enabled, the triacs illuminate the lamps until the AC voltage crosses zero. They must be constantly re-enabled to keep the lamps on.
The zero-cross circuit tells the CPU when the AC voltage is near zero.
Alternating current (AC) rapidly changes between a positive and negative voltage many times per second. In the US, the frequency is 60Hz, which means that the voltage is near zero about once every 8.33ms. Outside the US, line voltage is 50Hz and so zero crossing occurs every 10ms.
The zero cross data is used to dim the general illumination.
Both the WPC and DCS sound boards are connected via a ribbon cable to the CPU board, which sends it both read and write commands. The actual values vary greatly depending on the board type. These boards are intelligent and have processors running their own operating system dedicated to sound tasks.
1-byte or 2-byte commands are written to request particular sounds to be played. The sound board stores all of the sound data on additional EPROMs, and has its own CPU that decodes the data and writes it to various audio devices.
The sound board can also send data back to the CPU, notably to tell it when a sound has finished playing, allowing the CPU to synchronize its actions to the sounds and music.
On all but the earliest games, flipper control is located on a separate board, called the Fliptronic Board. It has 8 drivers for up to 4 flippers. Half of the drivers switch high power 50V, used when initially turning on a flipper; the other half switch a lower 'holding' power that is adequate for keeping the flipper in the raised position for a long period of time. The board also supports 8 switches that can be read by the CPU board: 4 for the flipper buttons and 4 end-of-stroke (EOS) switches. The button switches are wired to the cabinet buttons. The EOS switches are mounted on the flipper and used to determine when the flippers are in the 'up' position, indicating that the lower power voltage can be used.
On pre-Fliptronic games, the flippers are hardwired to the cabinet buttons, so flipping occurs without any CPU involvement. The CPU can control a relay on the power driver board to cut flipper power, though.
On WPC-95, the Fliptronic Board was eliminated and its components moved elsewhere: switch inputs moved to the CPU board, and flipper outputs moved to the driver board.
Some games use an auxiliary driver board which allows up to 8 additional flashlamps/low power devices to be controlled. These machines must have the following line in the machine config:
The auxiliary board plugs into the slot formerly used by the alphanumeric display board; thus, alphanumeric games cannot use this. This port was later removed on WPC-95.
The dot matrix display is 128 columns x 32 rows. The display itself is very dumb and expects a serial bitstream of pixels to be clocked in. The controller board has the display RAM and the serialization logic.
The controller fetches 1 byte (8 pixels) every 32 CPU cycles (16 microseconds). At this rate, it takes 256 microseconds per row and a little more than 8 milliseconds per complete frame. Thus, the refresh rate is about 122MHz.
The display RAM holds 8KB. A full DMD bit plane requires 128x32 pixels, that is, 4096 bits, or 512 bytes. Thus, there is enough RAM to hold a total of 16 planes. At any time, at most two planes can be addressed by the CPU (changed to six in WPC-95).
The SRAM is designed to allow both the 6809 and the serial decoder to access it simultaneously, at nonoverlapping phases of the system clocks.
Bits are encoded within a byte such that the leftmost pixel is in the least significant bit. This is backwards from how binary numbers are normally visualized.
The DMD controller exposes the following registers:
Says which of the 16 pages is currently accessible at CPU address 0x3800.
Says which of the 16 pages is currently accessible at CPU address 0x3A00.
The visible page register, WPC_DMD_ACTIVE_PAGE, holds the page number of the frame that should be clocked to the display. Writing to this register does not take effect immediately but instead at the beginning of the next vertical retrace.
The controller keeps track of which row is currently being refreshed, and makes this accessible to the CPU by reading the WPC_DMD_SCANLINE register. Values range from 0 to 31.
The CPU can also write to WPC_DMD_SCANLINE to request an FIRQ interrupt to be generated when the current scanline reaches a certain value. This is used to implement shading: the active page buffer is rapidly changed between different bit planes at different frequencies to simulate color. Because there is latency between the time that FIRQ is generated and the CPU can respond to it, this writable register can compensate for that delay and help to ensure that flipping occurs as fast as possible.
This section describes the WPC memory map in detail. In particular, it gives the function of each of the WPC ASIC registers, along with the names given to them by FreeWPC.